Multimedia Reconfigurable Hardware Design Space Exploration

In this paper we consider a set of multimedia applications and investigate the potential performance impact a reconfigurable microcoded processor can provide when added to a general purpose core processor. In a design space exploration, considering MPEG2 and JPEG benchmarks, we investigate performance boundaries, memory bottlenecks and the influence the core and reconfigurable processor communication has on performance. Under some realistic scenarios and serial FPGA execution, it is shown that a 53 % cycle reduction is expected when comparing a design having a core processor and a design when the core processor is augmented with a reconfigurable microcoded engine. In addition, we have found that transferring parameters between the core processor and the reconfigurable processor may not severely influence the overall performance. Finally we investigated the memory bandwidth for operations mapped automatically on FPGA. The case study indicates that small latency DCT hardware design performs well when interfaced with 512 bytes/cycle. Our studies also indicate that about 64 bytes/cycle will support high speed execution for SAD and IDCT.